Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Synchronizing Large VLSI Processor Arrays
IEEE Transactions on Computers
Signal resynchronization in VLSI for systems
Integration, the VLSI Journal
Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Transputer reference manual
IEEE Transactions on Computers
Efficiency of Synchronous Versus Asynchronous Distributed Systems
Journal of the ACM (JACM)
Reliability Issues in Computing System Design
ACM Computing Surveys (CSUR)
Introduction to VLSI Systems
Delay analysis of VLSI interconnections using the diffusion equation model
DAC '94 Proceedings of the 31st annual Design Automation Conference
Properties of Generalized Branch and Combine Clock Networks
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Computers
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
High Speed Externally Asynchronous/ Internally Clocked Systems
IEEE Transactions on Computers
Data-Driven Control Scheme for Linear Arrays: Application to a Stable Insertion Sorter
IEEE Transactions on Parallel and Distributed Systems
Scalability of Programmable FIR Digital Filters
Journal of VLSI Signal Processing Systems
Vector Transfer by Self-Tested Self-Synchronization for Parallel Systems
IEEE Transactions on Parallel and Distributed Systems
Statistical skew modeling for general clock distribution networks in presence of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical Carry Lookahead Adders
IEEE Transactions on Computers
Timing closure through a globally synchronous, timing partitioned design methodology
Proceedings of the 41st annual Design Automation Conference
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Theory of Generalized Branch and Combine Clock Networks
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
A NUMA architecture for parallel structures
MIC '07 Proceedings of the 26th IASTED International Conference on Modelling, Identification, and Control
Deadlock detection in automata arrays
MIC '07 Proceedings of the 26th IASTED International Conference on Modelling, Identification, and Control
A synchronization model for automata arrays
MIC '08 Proceedings of the 27th IASTED International Conference on Modelling, Identification and Control
Pipelining communications in large VLSI/ULSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Continuous advances in VLSI technology have made it possible to implement a system on a chip. One consequence of this is that the system will use a homogeneous technology for interconnections, gates, and synchronizers. Another consequence is that the system size and operation speed increase, which leads to increased problems with timing and synchronization. System and delay models necessary for the study of time performances of synchronous and asynchronous systems are developed. Clock skew is recognized as a key factor for the performance of synchronous systems. A mode of clocking that reduces the clock skew substantially is proposed and examined. Time penalty introduced by synchronizers is recognized as a key factor for the performance of asynchronous systems. This parameter is expressed in terms of system parameters. Different techniques and recommendations concerning performance improvement of synchronous and asynchronous systems are discussed.