Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Performance of Synchronous and Asynchronous Schemes for VLSI Systems
IEEE Transactions on Computers
A buffer distribution algorithm for high-performance clock net optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
AMULET1: An Asynchronous ARM Microprocessor
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Introduction to VLSI Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimal buffer insertion in clock trees with skew and slew rate constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Communications between processing elements (PEs) in very large scale parallel systems become more challenging as the function and speed of the PEs improve continuously. Clocked I/O ports may malfunction if data read failure occurs due to clock skew. There are many drawbacks in global clock distribution utilized to reduce the clock skew. This paper addresses a self-tested self-synchronization (STSS) method for vector transfer between PEs. A test signal is added to remove the data read failure. The advantages of this method are: very high data throughout, less power consumption in clock distribution, no constraints on clock skew and system scale, easy in design, less latency. A failure zone concept is used to characterize the behavior of storage elements. By using a jitter injected test signal, a robust vector transfer between PEs with arbitrary clock phases is achieved and the headache problem of the global synchronization is avoided.