An improved algorithm for minimum-area retiming
DAC '97 Proceedings of the 34th annual Design Automation Conference
Vector Transfer by Self-Tested Self-Synchronization for Parallel Systems
IEEE Transactions on Parallel and Distributed Systems
Marsh: min-area retiming with setup and hold constraints
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Efficient minarea retiming of large level-clocked circuits
Proceedings of the conference on Design, automation and test in Europe
Optimization of synchronous circuits
Logic Synthesis and Verification
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Sequential delay budgeting with interconnect prediction
Proceedings of the 2003 international workshop on System-level interconnect prediction
Variables bounding based retiming algorithm
Journal of Computer Science and Technology
Delay budgeting in sequential circuit with application on FPGA placement
Proceedings of the 40th annual Design Automation Conference
Timing Correction and Optimization with Adaptive Delay Sequential Elements
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Minimum-Area Sequential Budgeting for FPGA
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Sequential delay budgeting with interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
In-Circuit Self-Tuning of Clock Latencies
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Deriving a new efficient algorithm for min-period retiming
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A practical cut-based physical retiming algorithm for field programmable gate arrays
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficient retiming algorithm under setup and hold constraints
Proceedings of the 43rd annual Design Automation Conference
Self-tuning adaptive delay sequential elements
Microelectronics Journal
A new efficient retiming algorithm derived by formal manipulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A general model for performance optimization of sequential systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An efficient incremental algorithm for min-area retiming
Proceedings of the 45th annual Design Automation Conference
Scalable min-register retiming under timing and initializability constraints
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SPIRE: a retiming-based physical-synthesis transformation system
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.03 |
The introduction of clock skew at an edge-triggered flip-flop has an effect that is similar to the movement of the flip-flop across combinational logic module boundaries, and these are continuous and discrete optimizations with the same effect. While this fact has been recognized before, this paper, for the first time, utilizes this information to find an optimal retiming. The clock period is guaranteed to be at most one gate delay larger than the optimal clock period found using skew alone; note that since skew is a continuous optimization, it is possible that the optimal period may not be achievable. The method views the circuit hierarchically, first solving the clock skew problem at one level above the gate level, and then using local transformations at the gate level to perform retiming for the optimal clock period. The solution is thus divided into two phases. In Phase A, the clock skew optimization problem is solved with the objective of minimizing the clock period, while ensuring that the difference between the maximum and the minimum skew is minimized. Next, in Phase B, retiming is employed and some flip-flops are relocated across gates in an attempt to set the values of all skews to be as close to zero as possible