Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Optimizing two-phase, level-clocked circuitry
Journal of the ACM (JACM)
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Functional correlation analysis in crosstalk induced critical paths identification
Proceedings of the 38th annual Design Automation Conference
Driver modeling and alignment for worst-case delay noise
Proceedings of the 38th annual Design Automation Conference
False coupling interactions in static timing analysis
Proceedings of the 38th annual Design Automation Conference
On convergence of switching windows computation in presence of crosstalk noise
Proceedings of the 2002 international symposium on Physical design
Clock schedule verification with crosstalk
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Switching window computation for static timing analysis in presence of crosstalk noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On the performance of level-clocked circuits
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing analysis with crosstalk is a fixpoint on a complete lattice
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Static timing analysis for level-clocked circuits in the presence of crosstalk
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Latches are extensively used in high-performance sequential circuit designs to achieve high frequencies because of their good performance and time borrowing feature. However, the amount of timing uncertainty due to crosstalk accumulated through latches could be larger than the benefit gained by time borrowing. In this paper, we show that the trade-off between a latch and a flop can be leveraged in a sequential circuit design with crosstalk, so that the clock period is minimized by selecting a configuration of mixed latches and flops. A circular time representation is proposed to make coupling detection easier and more efficient. Experiments on our heuristic algorithm for finding an optimal configuration of mixed latches and flops showed promising results.