Certified timing verification and the transition delay of a logic circuit
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Digital sensitivity: predicting signal interaction using functional analysis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Identification of Crosstalk Switch Failures in Domino CMOS Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Noise Library Characterization for Large Capacity Static Noise Analysis Tools
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Neighboring line switching can contribute to a large portion of the delay of a line for today's deep submicron designs. In order to avoid excessive conservatism in static timing analysis, it is important to determine if aggressor lines can potentially switch simultaneously with the victim. In this paper, we present a comprehensive ATPG-based approach that uses functional information to identify valid interactions between coupled lines. Our algorithm accounts for glitches on aggressors that can be caused by static and dynamic hazards in the circuit. We present results on several benchmark circuits that show the value of considering functional information to reduce the conservatism associated with worst-case coupled line switching assumptions during static timing analysis.