Noise in deep submicron digital design
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Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 40th annual Design Automation Conference
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Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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CMOS Digital Integrated Circuits Analysis & Design
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Noise glitches can cause timing degradation in switching nodes or incorrect transitions in steady-state or "quiet" nodes. These incorrect transitions can propagate through the circuit, and can create functional errors or failures. This paper presents both a method and a practical implementation technique for accurately and efficiently characterizing and modeling the propagation of noise glitches through a cell within an integrated circuit. A characterization methodology is developed to generate Noise Immunity Criteria (NIC) and Noise Propagation Tables (NPT) for a given cell library. The resulting look-up tables are appended to any standard gate-level library to be utilized by Static Timing and Noise Analysis (STNA) tools.