Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
Estimation of the likelihood of capacitive coupling noise
Proceedings of the 39th annual Design Automation Conference
Conquering Noise in Deep-Submicron Digital ICs
IEEE Design & Test
Capturing crosstalk-induced waveform for accurate static timing analysis
Proceedings of the 2003 international symposium on Physical design
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Weibull Based Analytical Waveform Model
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Analytical models for crosstalk excitation and propagation in VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Noise Library Characterization for Large Capacity Static Noise Analysis Tools
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An efficient static algorithm for computing the soft error rates of combinational circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Accurate waveform modeling using singular value decomposition with applications to timing analysis
Proceedings of the 44th annual Design Automation Conference
Device and architecture concurrent optimization for FPGA transient soft error rate
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A robust finite-point based gate model considering process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A noniterative equivalent waveform model for timing analysis in presence of crosstalk
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Constrained aggressor set selection for maximum coupling noise
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk waveform modeling using wave fitting
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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To analyze the failure of a CMOS circuit due to glitches induced by capacitive crosstalk, noise immunity curves (a.k.a. noise rejection curve) must be characterized. However, noise waveform models currently used for characterization such as ideal triangle and trapezoid can underestimate the propagated noise pulse by over 20% and result in missed violations. We provide an analytical solution to fit any given crosstalk noise waveform to a Weibull function, which can generate identical propagated glitch heights compared to SPICE, resulting in accurate noise immunity curves.