Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Practical Issues of Interconnect Analysis in Deep Submicron Integrated Circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full-chip verification of UDSM designs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The deep sub-micron signal integrity challenge
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Functional correlation analysis in crosstalk induced critical paths identification
Proceedings of the 38th annual Design Automation Conference
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Reliable and energy-efficient digital signal processing
Proceedings of the 39th annual Design Automation Conference
IEEE Micro
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Analysis of Interconnect Crosstalk Defect Coverage of Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Noise Library Characterization for Large Capacity Static Noise Analysis Tools
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Analytical modeling of crosstalk noise waveforms using Weibull function
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Probabilistic arithmetic and energy efficient embedded signal processing
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Energy-aware probabilistic multiplier: design and analysis
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Crosstalk noise reduction in synthesized digital logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A dynamic jitter model to evaluate uncertainty trends with technology scaling
Integration, the VLSI Journal
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Design methodologies for digital integrated circuits are ultimately concerned with validating a design against metrics which ensure functionality, testability, and that the design satisfies power and timing requirements. Electronic design automation (EDA) tools and techniques have been developed to analyze each of these metrics. With technology scaling and increasing clock frequencies, noise and signal integrity are becoming important new design concerns in verifying functionality and accurately predicting timing. In this article, we describe a new metric for verifying functionality in the presence of noise, noise stability, and a static noise analysis methodology to verify it. In addition, we describe the effects of noise on delay and how these can be considered in the context of static timing analysis.