A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Conquering Noise in Deep-Submicron Digital ICs
IEEE Design & Test
Low Power Error Resilient Encoding for On-Chip Data Buses
Proceedings of the conference on Design, automation and test in Europe
Energy reduction in VLSI computation modules: an information-theoretic approach
IEEE Transactions on Information Theory
A communication-theoretic design paradigm for reliable SOCs
Proceedings of the 41st annual Design Automation Conference
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Performance driven reliable link design for networks on chips
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Energy-efficient soft error-tolerant digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reduction of detected acceptable faults for yield improvement via error-tolerance
Proceedings of the conference on Design, automation and test in Europe
Power and reliability management of SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A case study in reliability-aware design: a resilient LDPC code decoder
Proceedings of the conference on Design, automation and test in Europe
Design and implementation of cost-effective probabilistic-based noise-tolerant VLSI circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect
Microelectronics Journal
What is stochastic computation?
ACM SIGDA Newsletter
Stochastic networked computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and analysis of isolated noise-tolerant (INT) technique in dynamic CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting input variations for energy reduction
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
| Hi-index | 4.10 |
To increase processor performance, the microprocessor industry is scaling feature sizes into the deep submicron and sub-100-nanometer regime. The recent emergence of noise and the dramatic increase in process variations have raised serious questions about using nanometer process technologies to design reliable, low-power, high-performance computing systems.The design and electronic design automation communities must work closely with the process engineering community to address these problems. Specifically, researchers must explore the tradeoffs between reliability and energy efficiency at the device, circuit, architectural, algorithmic, and system levels.