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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Process variability is an emerging problem that is becoming worse with each new technology node. Its impact on the performance and energy of memory organizations is severe and degrades the system-level parametric yield. In this paper we propose a broadly applicable system-level technique that can guarantee parametric yield on the memory organization and which minimizes the energy overhead associated to variability in the conventional design process. It is based on offering configuration capabilities at the memory-level and exploiting them at the system-level. This technique can decrease by up to a factor of 5 the energy overhead that is introduced by state-of-the-art process variability compensation techniques, including statistical timing analysis. In this way we obtain results close to the ideal nominal design again.