Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies
Proceedings of the 2003 international symposium on Low power electronics and design
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Very wide register: an asymmetric register file organization for low power embedded processors
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and future trend of short-circuit power
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fanout optimization algorithm based on the effort delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a formalized synthesis methodology for variable tapered buffer chains achieving Pareto optimal Energy-Delay (E/D) trade-offs. Much work has been done for variable tapered buffer chain design explicitly targeting energy (and/or area) minimization for a given timing constraint. In contrast this work presents an automated methodology capable of providing all existing variable tapered buffer configurations achieving Pareto optimal trade-offs in the E/D space for the full feasible range of these two metrics together with a discussion of the practically achievable trade-off range. We also provide a practical case study that illustrates the application of our techniques in load dominated logical blocks such as decoders, drivers in SRAMs and Register Files (RF) as well as interconnect buffers. We have validated our design technique via SPICE simulations based on 65 and 32 nm CMOS technology and applied it for the design and fine tuning of run-time switchable buffers within these blocks, confirming that a very wide range in delay and energy reduction (up to 30%) can be achieved when compared to solely speed optimized buffer design.