Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Predicting short circuit power from timing models
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Constructing Current-Based Gate Models Based on Existing Timing Library
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power optimal MTCMOS repeater insertion for global buses
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Timing optimization in logic with interconnect
Proceedings of the 2008 international workshop on System level interconnect prediction
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Power consumption of logic circuits in ambipolar carbon nanotube technology
Proceedings of the Conference on Design, Automation and Test in Europe
On-chip interconnect analysis of performance and energy metrics under different design goals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving System Energy Efficiency with Memory Rank Subsetting
ACM Transactions on Architecture and Code Optimization (TACO)
Two-Phase clocking and a new latch design for low-power portable applications
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
ACM Transactions on Architecture and Code Optimization (TACO)
Modeling of energy dissipation in RLC current-mode signaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.03 |
A closed-form expression for short-circuit power dissipation of CMOS gates is presented which takes short-channel effects into consideration. The calculation results show good agreement with the SPICE simulation results over wide range of load capacitance and channel length. The change in the short-circuit power, PS, caused by the scaling in relation to the charging and discharging power, PD , is discussed and it is shown that basically power ratio, PS /(PD+PS), will not change with scaling if V TH/VDD is kept constant. This paper also handles the short-circuit power of series-connected MOSFET structures which appear in NAND and other complex gates