On-chip interconnect analysis of performance and energy metrics under different design goals

Authors:
Ling Zhang;Yulei Zhang;Hongyu Chen;Bo Yao;Kevin Hamilton;Chung-Kuan Cheng
Affiliations:
Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA;Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA;-;Mentor Graphics Corporation, Wilsonville, OR;Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA;Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2011

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Abstract

As semiconductor process technology scales down, interconnect planning presents ever-greater challenges to designers. In this paper, we analyze, evaluate, and compare various metrics with optimized wire configurations in the contexts of different design criteria: delay minimization, delay-power minimization, and delay2 -power minimization. We show how various design criteria influence the configuration, performance, and power consumption of repeated wires.