Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Effects of global interconnect optimizations on performance estimation of deep submicron design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Explicit gate delay model for timing evaluation
Proceedings of the 2003 international symposium on Physical design
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Replacing global wires with an on-chip network: a power analysis
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Wire sizing with scattering effect for nanoscale interconnection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
System level design paradigms: Platform-based design and communication synthesis
Proceedings of the 41st annual Design Automation Conference
Languages and tools for hybrid systems design
Foundations and Trends in Electronic Design Automation
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A global wiring paradigm for deep submicron design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A methodology for constraint-driven synthesis of on-chip communications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case performance prediction under supply voltage and temperature variation
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Accurate predictive interconnect modeling for system-level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
On-chip interconnect analysis of performance and energy metrics under different design goals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A tree-based topology synthesis for on-chip network
Proceedings of the International Conference on Computer-Aided Design
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Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level optimizations, such as network-on-chip (NoC) synthesis, are inaccurate in the presence of deep-submicron effects. In this paper, we propose new, highly accurate models for delay and power in buffered interconnects; these models are usable by system-level designers for existing and future technologies. We present a general and transferable methodology to construct our models from a wide variety of reliable sources (Liberty, LEF/ITF, ITRS, PTM, etc.). The modeling infrastructure, and a number of characterized technologies, are available as open source. Our models comprehend key interconnect circuit and layout design styles, and a power-efficient buffering technique that overcomes unrealities of previous delay-driven buffering techniques. We show that our models are significantly more accurate than previous models for global and intermediate buffered interconnects in 90nm and 65nm foundry processes - essentially matching signoff analyses. We also integrate our models in the COSI-OCC synthesis tool and show that the more accurate modeling significantly affects optimal/achievable architectures that are synthesized by the tool. The increased accuracy provided by our models enables system-level designers to obtain better assessments of the achievable performance/power/area tradeoffs for (communication-centric aspects of) system design, with negligible setup and overhead burdens.