AWESpice: a general tool for the accurate and efficient simulation of interconnect problems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Transient simulation of lossy interconnect
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Waveform moment methods for improved interconnection analysis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Efficient transient simulation of lossy interconnect
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Digital systems engineering
Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Figures of merit to characterize the importance of on-chip inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Driver modeling and alignment for worst-case delay noise
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Analysis of Multiconductor Transmission Lines
Analysis of Multiconductor Transmission Lines
Full-chip, three-dimensional, shapes-based RLC extraction
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer insertion for noise and delay optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Investigation of performance metrics for interconnect stack architectures
Proceedings of the 2004 international workshop on System level interconnect prediction
Coding for system-on-chip networks: a unified framework
Proceedings of the 41st annual Design Automation Conference
Joint Equalization and Coding for On-Chip Bus Communication
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime
Proceedings of the 2006 international workshop on System-level interconnect prediction
On optimal ordering of signals in parallel wire bundles
Integration, the VLSI Journal
Global interconnections in FPGAs: modeling and performance analysis
Proceedings of the 2008 international workshop on System level interconnect prediction
Proceedings of the 2008 international workshop on System level interconnect prediction
Interconnect modeling for improved system-level design optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Bandwidth-centric optimisation for area-constrained links with crosstalk avoidance methods
Proceedings of the conference on Design, automation and test in Europe
Power consumption of fault tolerant busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimal-power, delay-balanced SMART repeaters for global interconnects in the nanometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective shielding technique to eliminate crosstalk transitions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bus energy consumption for multilevel signals
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate predictive interconnect modeling for system-level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Throughput optimization for area-constrained links with crosstalk avoidance methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Joint equalization and coding for on-chip bus communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power, high-speed transceivers for network-on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switching sensitive driver circuit to combat dynamic delay in on-chip buses
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Fibonacci codes for crosstalk avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In a parallel multiwire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Using closed-form equations that map the geometry to the wire parasitics and empirical switch factor based delay models that show how repeaters can be optimized to compensate for dynamic effects, we devise a method of analysis for optimizing throughput over a given metal area. This analysis is used to show that there is a clear optimum configuration for the wires which maximizes the total bandwidth. Additionally, closed form equations are derived, the roots of which give close to optimal solutions. It is shown that for wide buses, the optimal wire width and spacing are independent of the total width of the bus, allowing easy optimization of on-chip buses. Our analysis and results are valid for lossy interconnects as are typical of wires in sub-micron technologies.