Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Reducing bus delay in submicron technology using coding
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Engineering Mathematics
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimization of Crosstalk Noise, Delay and Power Using a Modi.ed Bus Invert Technique
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Exploiting ECC Redundancy to Minimize Crosstalk Impact
IEEE Design & Test
Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Throughput optimization for area-constrained links with crosstalk avoidance methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The effect of crosstalk avoidance codes on the throughput of fixed width communication channels is studied. Closed form expressions of the throughput which incorporate the dimensions of the interconnects and the wires overheads by such techniques are derived for lines under different buffering conditions. These formulae are utilised to optimise the bandwidth of fixed width parallel buses under different latency and reliability constraints. Our results are confirmed by the simulations we have performed in Spectre for a UMC CMOS 90nm technology.