Joint Equalization and Coding for On-Chip Bus Communication
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A low-power bus design using joint repeater insertion and coding
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Delay and peak power minimization for on-chip buses using temporal redundancy
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
An energy-efficient temporal encoding circuit technique for on-chip high performance buses
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Low-power bus encoding using an adaptive hybrid algorithm
Proceedings of the 43rd annual Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Exploiting on-chip data behavior for delay minimization
Proceedings of the 2007 international workshop on System level interconnect prediction
A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Bus encoding schemes for minimizing delay in VLSI interconnects
Proceedings of the 20th annual conference on Integrated circuits and systems design
Selective shielding: a crosstalk-free bus encoding technique
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 international workshop on System level interconnect prediction
Forbidden transition free crosstalk avoidance CODEC design
Proceedings of the 45th annual Design Automation Conference
Bus encoding for simultaneous delay and energy optimization
Proceedings of the 13th international symposium on Low power electronics and design
Bandwidth-centric optimisation for area-constrained links with crosstalk avoidance methods
Proceedings of the conference on Design, automation and test in Europe
Energy efficient and high speed on-chip ternary bus
Proceedings of the conference on Design, automation and test in Europe
Data handling limits of on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective shielding technique to eliminate crosstalk transitions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay-efficient bus encoding techniques
Microprocessors & Microsystems
Reliable network-on-chip design for multi-core system-on-chip
The Journal of Supercomputing
Efficient on-chip crosstalk avoidance CODEC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information theoretic modeling and analysis for global interconnects with process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient CODEC designs for crosstalk avoidance codes based on numeral systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Joint equalization and coding for on-chip bus communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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Capacitive crosstalk between adjacent wires in long on-chip buses significantly increases propagation delay in the deep submicron regime. A high-speed bus can be designed by eliminating crosstalk delay through bus encoding. In this paper, we present an overview of the existing coding schemes and show that they require either a large wiring overhead or complex encoder-decoder circuits. We propose a family of codes referred to as overlapping codes that reduce both overheads. We construct two codes from this family and demonstrate their superiority over existing schemes in terms of area and energy dissipation. Specifically, for a 1-cm 32-bit bus in 0.13-µm CMOS technology, we present a 48-wire solution that has 1.98x speed-up, 10% energy savings and requires 20% less area than shielding.