Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
High Speed VLSI Interconnections: Modeling, Analysis, and Simulation
High Speed VLSI Interconnections: Modeling, Analysis, and Simulation
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An Automated Shielding Algorithm and Tool For Dynamic Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Interconnect modeling and optimization in deep sub-micron technologies
Interconnect modeling and optimization in deep sub-micron technologies
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
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In this paper, we propose a novel temporal encoding circuit for generic on-chip buses that enables higher performance while reducing peak energy, average energy and peak current. The proposed circuit dynamically generates shield signals depending on the current and previous state of input data signals to eliminate the worst-case coupling-transitions between adjacent wires. Comparisons to standard on-chip buses of various lengths with optimal repeater insertion in the 0.18-?m CMOS technology show that on-chip buses encoded by such circuit can achieve up to 23% increase in performance, and also provide gains in peak energy (up to 56%) and peak current (up to 60%) at all delay targets. The simulation results of various random input data streams show that the temporally encoded buses obtain up to 44% average energy savings over an optimal standard repeater bus.