Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two dimensional codes for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Energy-efficiency in presence of deep submicron noise
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power estimation for architectural exploration of HW/SW communication on system-level buses
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Synthesis of low-overhead interfaces for power-efficient communication over wide buses
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Information-theoretic bounds on average signal transition activity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
Reducing Address Bus Transitions for Low Power Memory Mapping
EDTC '96 Proceedings of the 1996 European conference on Design and Test
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Some Issues in Gray Code Addressing
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Routing methodology for minimizing 1nterconnect energy dissipation
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Coupling-aware high-level interconnect synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Weight-Based Bus-Invert Coding for Low-Power Applications
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Energy-reliability trade-off for NoCs
Networks on chip
A dictionary-based en/decoding scheme for low-power data buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Reduction of coupling effects by optimizing the 3-D configuration of the routing grid
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Minimization of Crosstalk Noise, Delay and Power Using a Modi.ed Bus Invert Technique
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Coding for system-on-chip networks: a unified framework
Proceedings of the 41st annual Design Automation Conference
Resource-constrained low-power bus encoding with crosstalk delay elimination
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Low-power instruction bus encoding for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime
Proceedings of the 2006 international workshop on System-level interconnect prediction
Multi-parametric improvements for embedded systems using code-placement and address bus coding
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A variation-aware low-power coding methodology for tightly coupled buses
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Partitioned bus coding for energy reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Delay and peak power minimization for on-chip buses using temporal redundancy
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
An energy-efficient temporal encoding circuit technique for on-chip high performance buses
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Bus encoding schemes for minimizing delay in VLSI interconnects
Proceedings of the 20th annual conference on Integrated circuits and systems design
Energy efficiency bounds of pulse-encoded buses
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Forbidden transition free crosstalk avoidance CODEC design
Proceedings of the 45th annual Design Automation Conference
Timing-aware power-optimal ordering of signals
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy efficient and high speed on-chip ternary bus
Proceedings of the conference on Design, automation and test in Europe
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal
Reliable network-on-chip design for multi-core system-on-chip
The Journal of Supercomputing
GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses
Microprocessors & Microsystems
Efficient on-chip crosstalk avoidance CODEC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Approximate arithmetic coding for bus transition reduction in low power designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
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Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed to minimize coupled switchings which dominate the on-chip bus power consumption. The coupling-driven bus invert method use slim encoder and decoder architecture to minimize the hardware overhead. Experimental results indicate that our encoding methods save effective switchings as much as 30% in an 8-bit bus with one-cycle redundancy.