Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Narrow bus encoding for low power systems
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Partial bus-invert coding for power optimization of application-specific systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
An analysis of the behavior of a class of genetic adaptive systems.
An analysis of the behavior of a class of genetic adaptive systems.
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Shift Invert Coding (SINV) for Low Power VLSI
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Low-power bus encoding using an adaptive hybrid algorithm
Proceedings of the 43rd annual Design Automation Conference
HW/SW partitioning using discrete particle swarm
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Tunable and Energy Efficient Bus Encoding Techniques
IEEE Transactions on Computers
Approximate arithmetic coding for bus transition reduction in low power designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Two main sources for power dissipation in parallel buses are data transitions on each wire and coupling between adjacent wires. So far, many techniques have been proposed for reducing the self and coupling powers. Most of these methods utilize one (or more) control bit(s) to manage the behavior of data transitions on the parallel bus. In this paper, we propose a new coding scheme, referred to as GPH, to reduce power dissipation of these control bits. GPH coding scheme employs partitioned Bus Invert and Odd Even Bus-Invert coding techniques. This method benefits from Particle Swarm Optimization (PSO) algorithm to efficiently partition the bus. In order to reduce self and coupling powers of the control bits, it finds partitions with similar transition behaviors and groups them together. One extra control bit is added to each group of partitions. Properly managing number of transitions on control bits of each partition and that of each group, GPH reduces total power consumption, including coupling power. It also locates control bits of each partition such that total power consumption is minimized. We evaluate the efficiency of the proposed method for coding data and address buses under various hardware platforms. Experimental results show 43% average power saving in coded data compared to the original one. We also show the prominence of our coding scheme over previously proposed techniques.