Bus encoding schemes for minimizing delay in VLSI interconnects
Proceedings of the 20th annual conference on Integrated circuits and systems design
An optimization strategy for low energy and high performance for the on-chip interconnect signalling
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses
Microprocessors & Microsystems
Hi-index | 0.00 |
This talk will first review the challenges in the design of emerging complex systems-on-a-chip (SoC) at STMicroelectronics, from the perspective of our customers' requirements. We then present an approach to effectively integrate heterogenous parallel ...