Bus encoding schemes for minimizing delay in VLSI interconnects

Authors:
K. S. Sainarayanan;Chittarsu Raghunandan;M. B. Srinivas
Affiliations:
International Institute of Information Technology (IIIT): Hyderabad, HYDERABAD, India;International Institute of Information Technology (IIIT): Hyderabad, HYDERABAD, India;International Institute of Information Technology (IIIT): Hyderabad, HYDERABAD, India
Venue:
Proceedings of the 20th annual conference on Integrated circuits and systems design
Year:
2007

Citing 12
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Abstract

In deep-submicron (DSM) technology, shrinking wire size andreduced inter-wire spacing are leading to increased propagation delay of the on-chip interconnects. Various techniques, such as shielding and coding, etc., have been proposed to minimize this delay. This paper proposes a set of coding schemes (scheme 1, 2 and 3) to reduce the delay by incorporating spatial and temporal redundancy independently as well as combined. SPICE simulations are carried out for interconnect lines of different dimensions at various technology nodes (180, 130, 90 and 65 nm). Experimental results indicate that the proposed coding scheme-2 eliminates the crosstalk classes 4, 5 and 6, and reduces the delay by about 33-67% for 2, 5 and 10 mm lengthinterconnects.