On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Bus encoding schemes for minimizing delay in VLSI interconnects
Proceedings of the 20th annual conference on Integrated circuits and systems design
Multimode embedded compression codec engine for power-aware video coding system
IEEE Transactions on Circuits and Systems for Video Technology
Low-energy-transmission of data on submicron interconnects
WSEAS TRANSACTIONS on COMMUNICATIONS
Computers and Electrical Engineering
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Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucial to the performance and reliability of SoC designs. This paper presents a new on-chip bus encoding scheme targeting high performance generic SoC systems. In addition to its efficiency in terms of power, the scheme reduces delay faults by completely eliminating the most critical type of crosstalk coupling that causes three adjacent wires to undergo Miller-like transition simultaneously. The paper describes the technique, its implementation (using the widely adopted AMBA-AHB SoC bus standard) and provides results indicating between 24% to 38% energy saving for systems implemented in 0.18µm CMOS technology.