Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Resource-constrained low-power bus encoding with crosstalk delay elimination
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms
Computers and Electrical Engineering
Selective shielding: a crosstalk-free bus encoding technique
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Computers and Electrical Engineering
A low power crosstalk-free bus encoding using genetic algorithm
AICCSA '08 Proceedings of the 2008 IEEE/ACS International Conference on Computer Systems and Applications
Fault-tolerant dynamically reconfigurable NoC-based SoC
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
NoC Power Optimization Using a Reconfigurable Router
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Dynamic reconfiguration architectures for multi-context FPGAs
Computers and Electrical Engineering
Hardware-software co-synthesis of hard real-time systems with reconfigurable FPGAs
Computers and Electrical Engineering
Learning-based adaptation to applications and environments in a reconfigurable network-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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To solve two increasingly problematic issues, namely crosstalk interferences and wire power consumption, in a Network-on-Chip (NoC), Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC) is proposed. It includes a novel reconfigurable NoC design, four data encoding strategies, and an intelligent REasoning And Learning (REAL) framework for encoding strategy selection. Instead of pre-integrating all encoding strategies into a NoC at design time, REAL can configure PRESSNoC with an appropriate encoding method at run-time. Compared to baseline NoCs that use a fixed encoding method, the average benefit to overhead ratio of the PRESSNoC is greater by 88%, 39%, and 277%, at the interference, application, and system levels, respectively. Experiments show that at the same overheads of performance and hardware resources PRESSNoC induces a higher probability toward the reduction of crosstalk interferences and dynamic power consumption.