Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Leakage control with efficient use of transistor stacks in single threshold CMOS
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simultaneous shield insertion and net ordering under explicit RLC noise constraint
Proceedings of the 38th annual Design Automation Conference
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Design Challenges of Technology Scaling
IEEE Micro
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Static leakage reduction through simultaneous threshold voltage and state assignment
Proceedings of the 40th annual Design Automation Conference
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies
Proceedings of the 2003 international symposium on Low power electronics and design
Leakage-and crosstalk-aware bus encoding for total power reduction
Proceedings of the 41st annual Design Automation Conference
Design and CAD Challenges in sub-90nm CMOS Technologies
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Approaches to run-time and standby mode leakage reduction in global buses
Proceedings of the 2004 international symposium on Low power electronics and design
Reliable network-on-chip design for multi-core system-on-chip
The Journal of Supercomputing
Computers and Electrical Engineering
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Increased buffer insertion along on-chip global lines and the increasing contribution of leakage power have resulted in buffer leakage emerging as one of the chief contributors to system leakage power. In this paper, we present a novel power-gating scheme for repeaters on global bus lines that address the pressing problem of runtime leakage while simultaneously eliminating worst-case capacitive coupling between adjacent bus lines. We propose using a pulsed MTCMOS scheme that dynamically activates the bus system only when transmitting a signal. Additionally, a bus encoding scheme is used to eliminate worst-case coupling and thereby negate the power-gating and pulse generation performance penalty. We consider all sources of delay and leakage power, including that of the MTCMOS control circuitry. This technique can result in nearly a 30% reduction in total bus system power for low switching activities and up to 2.3X reduction in standby mode leakage with no reactivation delay penalty.