Low-power CMOS design through VTH control and low-swing circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Low Power Digital CMOS Design
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
Optimal Voltages and Sizing for Low Power
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Approaches to run-time and standby mode leakage reduction in global buses
Proceedings of the 2004 international symposium on Low power electronics and design
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies
Proceedings of the 2004 international symposium on Low power electronics and design
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A simple mechanism to adapt leakage-control policies to temperature
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Flip-flop energy/performance versus clock slope and impact on the clock network design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
Leveraging rule-based designs for automatic power domain partitioning
Proceedings of the International Conference on Computer-Aided Design
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This paper compares the effectiveness of different leakage control techniques in deep submicron (DSM) bulk CMOS technologies. Simulations show that the 3-5x increase in IOFF/mm per generation is offsetting the savings in switching energy obtained from technology scaling. We compare both the transistor IOFF reduction and ION degradation due to each technique for the 130nm-70nm technologies. Our results indicate that the effectiveness of leakage control techniques and the associated energy vs. delay tradeoffs depend on the ratio of switching to leakage energies for a given technology. We use our findings to design a 70nm low power word line driver scheme for a 256 entry, 64-bit register file (RF). As a result, the leakage (total) energy of the word line drivers is reduced by 3x(2.5x) and for the RF by up to 35%(25%) respectively.