A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies

Authors:
Bhaskar Chatterjee;Manoj Sachdev;Ram Krishnamurthy
Affiliations:
University of Waterloo, Waterloo, ON, Canada;University of Waterloo, Waterloo, ON, Canada;Intel Corp., Hillsboro, OR
Venue:
Proceedings of the 2004 international symposium on Low power electronics and design
Year:
2004

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Abstract

In this paper we present the design of a high performance 32-bit ALU for low power applications. We use dual power supply scheme and CPL logic for non-critical units of the ALU. In addition, latches with only n-MOS clocked transistors are used to interface logic operating at different power supplies and achieve static power free operation. Our simulation results indicate that, for the 180nm-65nm CMOS technologies it is possible to reduce the ALU total energy by 18%-24%, with minimal delay degradation. In addition, there is up to 22%-32% reduction in leakage power in the standby mode.