Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Estimation of sequential circuit activity considering spatial and temporal correlations
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Optimal Voltages and Sizing for Low Power
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies
Proceedings of the 2003 international symposium on Low power electronics and design
Selective gate-length biasing for cost-effective runtime leakage control
Proceedings of the 41st annual Design Automation Conference
Tradeoffs between date oxide leakage and delay for dual Tox circuits
Proceedings of the 41st annual Design Automation Conference
Approaches to run-time and standby mode leakage reduction in global buses
Proceedings of the 2004 international symposium on Low power electronics and design
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies
Proceedings of the 2004 international symposium on Low power electronics and design
A simple mechanism to adapt leakage-control policies to temperature
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power fanout optimization using multi threshold voltages and multi channel lengths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate oxide leakage and delay tradeoffs for dual-toxcircuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure
Journal of Computational Electronics
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Power optimization has become an important issue for high performance designs. One way to achieve low-power and high performance circuits is to use dual-threshold voltages. High threshold transistors can be used in non-critical paths to reduce the leakage power, while lower threshold voltage is used for transistors in critical path(s) to achieve high performance. This paper proposes two low power and high performance CMOS design techniques - multiple channel length (MLCMOS) and multiple oxide thickness (MoxCMOS), based on dual V th design technique. A comprehensive algorithm for selecting and assigning optimal transistor threshold voltage, channel length and oxide thickness is given. The simulation results on ISCAS benchmark circuits show that the total power consumption can be reduced by 21% for MLCMOS at low activity. Total power savings for MoxCMOS at low and high switching activities are about 42% and 24%, respectively.