Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Circuit-level techniques to control gate leakage for sub-100nm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Analysis and minimization techniques for total leakage considering gate oxide leakage
Proceedings of the 40th annual Design Automation Conference
Static leakage reduction through simultaneous threshold voltage and state assignment
Proceedings of the 40th annual Design Automation Conference
Optimizing CMOS Circuits for Low Power Using Transistor Reordering
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Circuit optimization for minimisation of power consumption under delay constraint
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Tradeoffs between date oxide leakage and delay for dual Tox circuits
Proceedings of the 41st annual Design Automation Conference
Tutorial 2: Leakage Issues in IC Design: Trends, Estimation, and Avoidance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
CMOS design near the limit of scaling
IBM Journal of Research and Development
Reducing power dissipation in CMOS circuits by signal probability based transistor reordering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A timing-constrained simultaneous global routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells
Microelectronics Journal
| Hi-index | 0.00 |
Gate oxide tunneling current (Igate) is comparable to subthreshold leakage current in CMOS circuits when the equivalent physical oxide thickness (Tox) is below 15 Å. Increasing the value of Tox reduces the leakage at the expense of increased delay, and hence a practical tradeoff between delay and leakage can be achieved by assigning one of two permissible Tox values to each transistor. In this paper, we propose an algorithm for dual- Tox assignment to optimize the total leakage power under delay constraints and generate a leakage/delay tradeoff curve. As compared to the case where all transistors are set to low Tox, our approach achieves an average leakage reduction of 86% under 100 nm models and 81% under 70 nm models. We also propose a transistor and pin reordering technique that has minimal layout impact to further reduce the total leakage current up to 12% and Igate up to 27% without incurring any delay penalty.