Node normalization and decomposition in low power technology mapping
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
A new approach to power estimation and reduction in CMOS digital circuits
Integration, the VLSI Journal
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Gate oxide leakage and delay tradeoffs for dual-toxcircuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper introduces novel transistor reordering schemes to reduce the expected or average dynamic power dissipation in CMOS circuits. The transistor reordering is based on the signal probability values at the inputs of the gates. The paper begins with a simple analytical model for the dynamic power dissipation in a static NAND gate. The model is used to derive an algorithm for transistor reordering which reduces dynamic power dissipation. A simulation technique for accurately measuring the power dissipation in NAND gates is also presented, along with the results of the reordering algorithm. A transistor reordering algorithm for CMOS complex gates is subsequently presented. Transistor reordering is found to be an effective way to reduce power dissipation in all of these circuits, with the reduction in dynamic power dissipation compared to the worst case configuration, being as high as 50% in some instances. The limited overhead associated with transistor reordering encourage its application as a low power design technique