Monte Carlo analysis of semiconductor devices: the DAMOCLES program
IBM Journal of Research and Development
CMOS scaling into the 21st century: 0.1 &mgr;m and beyond
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Analysis and minimization techniques for total leakage considering gate oxide leakage
Proceedings of the 40th annual Design Automation Conference
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Gate oxide leakage current analysis and reduction for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tradeoffs between date oxide leakage and delay for dual Tox circuits
Proceedings of the 41st annual Design Automation Conference
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Performance implications of single thread migration on a chip multi-core
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Self-biased charge sampling amplifier in 90nm CMOS for medical ultrasound imaging
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Throughput optimal task allocation under thermal constraints for multi-core processors
Proceedings of the 46th Annual Design Automation Conference
Impact of shrinking technologies on the activation function of neurons
ICANN'07 Proceedings of the 17th international conference on Artificial neural networks
Analysis and modeling of high performace and low power UTB SGOI devices scalable to sub 30 nm
CSS'10 Proceedings of the 4th international conference on Circuits, systems and signals
Gate oxide leakage and delay tradeoffs for dual-toxcircuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Inverter-based 1 V analog front-end amplifiers in 90 nm CMOS for medical ultrasound imaging
Analog Integrated Circuits and Signal Processing
Modeling and performance evaluation of UTB SGOI devices scalable to 22 nm technology node
WSEAS Transactions on Circuits and Systems
Analysis and modeling of high performance and low power UTB SGOI devices scalable to sub 30 nm
ICS'10 Proceedings of the 14th WSEAS international conference on Systems: part of the 14th WSEAS CSCC multiconference - Volume I
Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure
Journal of Computational Electronics
Eliminating energy of same-content-cell-columns of on-chip SRAM arrays
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Enabling cutting-edge semiconductor simulation through grid technology
LSSC'09 Proceedings of the 7th international conference on Large-Scale Scientific Computing
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Modeling the impact of permanent faults in caches
ACM Transactions on Architecture and Code Optimization (TACO)
| Hi-index | 0.00 |
Beginning with a brief review of CMOS scaling trends from 1 µm to 0.1 µm, this paper examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling. The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length. Both the standby power and the active power of a processor chip will increase precipitously below the 0.1-µm or 100-nm technology generation. To extend CMOS scaling to the shortest channel length possible while still gaining significant performance benefit, an optimized, vertically and laterally nonuniform doping design (superhalo) is presented. It is projected that room-temperature CMOS will be scaled to 20-nm channel length with the superhalo profile. Low-temperature CMOS allows additional design space to further extend CMOS scaling to near 10 nm.