Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

Authors:
Ashwani K. Rana;Narottam Chand;Vinod Kapoor
Affiliations:
Department of Electronics and Communication, National Institute of Technology, Hamirpur Hamirpur, India 177005;Department of Computer Science and Engineering, National Institute of Technology, Hamirpur Hamirpur, India 177005;Department of Electronics and Communication, National Institute of Technology, Hamirpur Hamirpur, India 177005
Venue:
Journal of Computational Electronics
Year:
2011

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Abstract

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behavior of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended source/drain region. It is found that optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering characteristic with a slight degradation in source/drain series resistance and effective gate capacitance.