Low power gate-level design with mixed-Vth (MVT) techniques
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Analysis and optimization of gate leakage current of power gating circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Digital Circuit Optimization via Geometric Programming
Operations Research
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DFT and minimum leakage pattern generation for static power reduction during test and burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure
Journal of Computational Electronics
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Two CMOS design techniques use dual threshold voltages to reduce power consumption while maintaining high performance. Simulation results show power savings of 21% for one technique at low activity, and for the other, 19% at high activity and 38% at low activity.