Logic-based 0-1 constraint programming
Logic-based 0-1 constraint programming
A high speed and low power SOL inverter using active body-bias
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Static power optimization of deep submicron CMOS circuits for dual VT technology
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Leakage control with efficient use of transistor stacks in single threshold CMOS
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Minimizing stand-by leakage power in static CMOS circuits
Proceedings of the conference on Design, automation and test in Europe
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Robust SAT-Based Search Algorithm for Leakage Power Reduction
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimization Trade-offs for Vector Volume and Test Power
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Power Reduction through Minimization of Scan Chain Transitions
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
ICTAI '05 Proceedings of the 17th IEEE International Conference on Tools with Artificial Intelligence
Exact and heuristic approaches to input vector control for leakage power reduction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Thermal and Power Management of Integrated Circuits (Series on Integrated Circuits and Systems)
Thermal and Power Management of Integrated Circuits (Series on Integrated Circuits and Systems)
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses
IEEE Design & Test
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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This paper presents a design for testability and minimum leakage pattern generation technique to reduce static power during test and burn-in for nanometer technologies. This technique transforms the minimum leakage pattern generation problem into a pseudo-Boolean optimization (PBO) problem. Nonlinear objective functions of leakage power are approximated by linear ones such that this problem can be solved efficiently by an existing PBO solver. A partitioning-based algorithm is applied for control point insertion and also CPU time reduction. Experimental results on the IEEE ISCAS'89 benchmark circuits using Taiwan Semiconductor Manufacturing Company 90-nm technology show that, for large circuits, the static power is reduced from 8.3% (without partition) to 17.47% (with 64 partitions). Besides, the overall CPU time is reduced from 3600 s (without partition) to 83 s (with 64 partitions). This technique reduces the static power without changing the manufacturing process or library cells.