Leakage control with efficient use of transistor stacks in single threshold CMOS
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Leakage control with efficient use of transistor stacks in single threshold CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DFT and minimum leakage pattern generation for static power reduction during test and burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose a new high speed and low power SOI inverter that can operate with efficient body-bias control and free supply voltage. The performance of the proposed circuit is evaluated by both the BSIM3SOI circuit simulator and the ATLAS device simulator, and then compared with other reported SOI circuits. The proposed circuit is shown to have excellent characteristics. At the supply voltage of 1.5V, the proposed circuit operates 27% faster than the conventional SOI circuit with the same power dissipation.