Leakage control with efficient use of transistor stacks in single threshold CMOS

Future performance challenges in nanometer design

Proceedings of the 38th annual Design Automation Conference

Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1,2

Proceedings of the 2002 international symposium on Low power electronics and design

Evaluating Run-Time Techniques for Leakage Power Reduction

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Gate leakage reduction for scaled devices using transistor stacking

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Leakage current reduction in CMOS VLSI circuits by input vector control

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Approaches to run-time and standby mode leakage reduction in global buses

Proceedings of the 2004 international symposium on Low power electronics and design

Dynamic Functional Unit Assignment for Low Power

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Reducing both dynamic and leakage energy consumption for hard real-time systems

Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems

Transistor-Level Optimization of Digital Designs with Flex Cells

Computer

Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Characterization and modeling of run-time techniques for leakage power reduction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems

An effective power mode transition technique in MTCMOS circuits

Proceedings of the 42nd annual Design Automation Conference

Dynamic functional unit assignment for low power

The Journal of Supercomputing

Exact and heuristic approaches to input vector control for leakage power reduction

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Technology mapping for low leakage power and high speed with hot-carrier effect consideration

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction

Proceedings of the 43rd annual Design Automation Conference

A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits

Proceedings of the 2006 international symposium on Low power electronics and design

Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations

CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems

A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Accurate energy breakeven time estimation for run-time power gating

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

A robust power gating structure and power mode transition strategy for MTCMOS design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DFT and minimum leakage pattern generation for static power reduction during test and burn-in

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)