Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage control with efficient use of transistor stacks in single threshold CMOS
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Standby power management for a 0.18μm microprocessor
Proceedings of the 2002 international symposium on Low power electronics and design
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Wireless sensor networks for habitat monitoring
WSNA '02 Proceedings of the 1st ACM international workshop on Wireless sensor networks and applications
Design Challenges of Technology Scaling
IEEE Micro
Sub-90nm technologies: challenges and opportunities for CAD
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate oxide leakage current analysis and reduction for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An ultra low-power processor for sensor networks
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Sensor Networks for Emergency Response: Challenges and Opportunities
IEEE Pervasive Computing
Energy Optimization of Subthreshold-Voltage Sensor Network Processors
Proceedings of the 32nd annual international symposium on Computer Architecture
An Ultra Low Power System Architecture for Sensor Network Applications
Proceedings of the 32nd annual international symposium on Computer Architecture
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
A study of low level vibrations as a power source for wireless sensor nodes
Computer Communications
On the impact of manufacturing process variations on the lifetime of sensor networks
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Minimal placement of bank selection instructions for partitioned memory architectures
ACM Transactions on Embedded Computing Systems (TECS)
Low-power TinyOS tuned processor platform for wireless sensor network motes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the Impact of Manufacturing Process Variations on the Lifetime of Sensor Networks
ACM Transactions on Embedded Computing Systems (TECS)
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Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for low-throughput, energy-constrained applications. Unlike traditional performance oriented applications, sensor network nodes are primarily constrained by operation lifetime, which is limited by power consumption. Advanced CMOS process technologies provide ever increasing transistor density and improved performance characteristics. However, shrinking feature size and decreasing threshold voltages also lead to significant increases in leakage current, which is especially troublesome for applications with significant idle times. This work investigates tradeoffs between leakage and active power for low-throughput applications. We study these issues across a range of process technologies on a computing architecture that provides explicit support for fine-grain leakage-control techniques such as Vdd-gating and adaptive body bias. We present a methodology for selecting design parameters, including choice of process technology, that makes the optimal tradeoff between active power and leakage power for a given workload. Our results show that leakage power will dominate the selection of process technology, and architectures that support advanced leakage control techniques at the circuit level will be essential. We argue that without advanced low-power architectures future nano-scale process technologies will not be suited for sensor network applications.