Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Reducing leakage in a high-performance deep-submicron instruction cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Low-leakage asymmetric-cell SRAM
Proceedings of the 2002 international symposium on Low power electronics and design
Compiler-directed instruction cache leakage optimization
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Exploiting program hotspots and code sequentiality for instruction cache leakage management
Proceedings of the 2003 international symposium on Low power electronics and design
IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Microarchitectural power modeling techniques for deep sub-micron microprocessors
Proceedings of the 2004 international symposium on Low power electronics and design
Low power gate-level design with mixed-Vth (MVT) techniques
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Reverse-body bias and supply collapse for low effective standby power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs
IEEE Transactions on Computers
Controlling leakage power with the replacement policy in slumberous caches
Proceedings of the 2nd conference on Computing frontiers
Leakage power optimization with dual-Vth library in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Total leakage power optimization with improved mixed gates
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Exploring the limits of leakage power reduction in caches
ACM Transactions on Architecture and Code Optimization (TACO)
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Locality analysis to control dynamically way-adaptable caches
MEDEA '04 Proceedings of the 2004 workshop on MEmory performance: DEaling with Applications , systems and architecture
Power-performance considerations of parallel computing on chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Dual-K Versus Dual-T Technique for Gate Leakage Reduction: A Comparative Perspective
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
PowerNap: An Efficient Power Management Scheme for Mobile Devices
IEEE Transactions on Mobile Computing
ACM Transactions on Embedded Computing Systems (TECS)
Throttling-Based Resource Management in High Performance Multithreaded Architectures
IEEE Transactions on Computers
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Design of mixed gates for leakage reduction
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Temperature-aware leakage minimization technique for real-time systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
Proceedings of the 4th international conference on Computing frontiers
A proposal to introduce power and energy notions in computer architecture laboratories
WCAE '07 Proceedings of the 2007 workshop on Computer architecture education
Compilation for compact power-gating controls
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A methodology for analysis and verification of power gated circuits with correlated results
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Cache leakage control mechanism for hard real-time systems
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Integration, the VLSI Journal
Minimizing leakage: what if every gate could have its individual threshold voltage?
AIAP'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: artificial intelligence and applications
Reducing leakage in power-saving capable caches for embedded systems by using a filter cache
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
Analysis of static and dynamic energy consumption in NUCA caches: initial results
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
Electronic Notes in Theoretical Computer Science (ENTCS)
Block remap with turnoff: a variation-tolerant cache design technique
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
RPM: a remote computer power management tool
International Journal of Computer Applications in Technology
Optimizing thread throughput for multithreaded workloads on memory constrained CMPs
Proceedings of the 5th conference on Computing frontiers
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
Leakage current optimization techniques during test based on don't care bits assignment
Journal of Computer Science and Technology
Microprocessors & Microsystems
Noninvasive leakage power tomography of integrated circuits by compressive sensing
Proceedings of the 13th international symposium on Low power electronics and design
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Sleepy stack leakage reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit
ACM Transactions on Embedded Computing Systems (TECS)
Analysis and design of a context adaptable SAD/MSE architecture
International Journal of Reconfigurable Computing
Dynamic reconfiguration architectures for multi-context FPGAs
Computers and Electrical Engineering
Power optimization with power islands synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Full custom low-power/high performance DDP-based Cobra-H64 cipher
Computers and Electrical Engineering
A cost-effective load-balancing policy for tile-based, massive multi-core packet processors
ACM Transactions on Embedded Computing Systems (TECS)
Automated power gating of registers using CoDeL and FSM branch prediction
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Applying statistical machine learning to multicore voltage & frequency scaling
Proceedings of the 7th ACM international conference on Computing frontiers
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Instruction scheduling for VLIW processors under variation scenario
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Design of low power multimode time-shared filters
ICICS'09 Proceedings of the 7th international conference on Information, communications and signal processing
International Journal of High Performance Systems Architecture
ULPFA: a new efficient design of a power-aware full adder
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Low power and high speed multiplier design with row bypassing and parallel architecture
Microelectronics Journal
Exploiting narrow-width values for thermal-aware register file designs
Proceedings of the Conference on Design, Automation and Test in Europe
Energy-aware packet and task co-scheduling for embedded systems
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
Leakage-efficient design of value predictors through state and non-state preserving techniques
The Journal of Supercomputing
Leakage-aware multiprocessor scheduling for low power
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Energy efficient joint scheduling and multi-core interconnect design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design research of the DES against power analysis attacks based on FPGA
Microprocessors & Microsystems
Quantitative analysis and optimization techniques for on-chip cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Design of MRAM based logic circuits and its applications
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Power-aware dynamic cache partitioning for CMPs
Transactions on high-performance embedded architectures and compilers III
Towards an adaptable multiple-ISA reconfigurable processor
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Wire topology optimization for low power CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BarrierWatch: characterizing multithreaded workloads across and within program-defined epochs
Proceedings of the 8th ACM International Conference on Computing Frontiers
Journal of Signal Processing Systems
Beyond Green: Evolution to Adaptability and Recyclability
GREENCOM '11 Proceedings of the 2011 IEEE/ACM International Conference on Green Computing and Communications
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Compiler-driven leakage energy reduction in banked register files
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
An FPGA power aware design flow
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
An optimization mechanism intended for static power reduction using dual-Vth technique
Journal of Electrical and Computer Engineering
Proceedings of the 49th Annual Design Automation Conference
Journal of Signal Processing Systems
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy efficient automotive networks: state of the art and challenges ahead
International Journal of Communication Networks and Distributed Systems
Power-efficient time-sensitive mapping in heterogeneous systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Triple-threshold static power minimization in high-level synthesis of VLSI CMOS
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Support for fine-grained synchronization in shared-memory multiprocessors
PaCT'07 Proceedings of the 9th international conference on Parallel Computing Technologies
Power devil: tool for power gating strategy selection
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
Analysis and Design of Low-Cost Bit-Serial Architectures for Motion Estimation in H.264/AVC
Journal of Signal Processing Systems
Towards a multiple-ISA embedded system
Journal of Systems Architecture: the EUROMICRO Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Unified performance and power modeling of scientific workloads
E2SC '13 Proceedings of the 1st International Workshop on Energy Efficient Supercomputing
VarEMU: an emulation testbed for variability-aware software
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
AMBER: adaptive energy management for on-chip hybrid video memories
Proceedings of the International Conference on Computer-Aided Design
Energy efficient computation: A silicon perspective
Integration, the VLSI Journal
Studying the code compression design space - A synthesis approach
Journal of Systems Architecture: the EUROMICRO Journal
PAAS: Power Aware Algorithm for Scheduling in High Performance Computing
UCC '13 Proceedings of the 2013 IEEE/ACM 6th International Conference on Utility and Cloud Computing
Hi-index | 4.11 |
Off-state leakage is static power, current that leaks through transistors even when they are turned off. The other source of power dissipation in today's microprocessors, dynamic power, arises from the repeated capacitance charge and discharge on the output of the hundreds of millions of gates in today'schips.Until recently, only dynamic power has been a significant source of power consumption, and Moore's law helped control it. However, power consumption has now become a primary microprocessor design constraint one that researchers in both industry and academia will struggle to overcome in the next few years.