Design Techniques for Gate-Leakage Reduction in CMOS Circuits
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
| Hi-index | 0.00 |
With the rapid proliferation of handheld and other mobile devices, electronic circuits need to reduce both operational and off-state power consumption. This is necessary for both the chips and the end products to be competitive in their respective markets. In this paper, details of an innovative solution that combines full-chip level capacity with transistor level accuracy is presented which integrated circuit designers can use to analyze and optimize circuits that employ a commonly used standby leakage current reduction technique. An advanced capability of this tool like its ability to simulate multiple operating modes of such circuits is discussed. This analysis approach was demonstrated to have very good correlation to both silicon and spice based measurements..