Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Managing multi-configuration hardware via dynamic working set analysis
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
Improving power efficiency of D-NUCA caches
ACM SIGARCH Computer Architecture News
Modeling of cache access behavior based on Zipf's law
Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture
International Journal of High Performance Systems Architecture
A majority-based control scheme for way-adaptable caches
Facing the multicore-challenge
Power-aware dynamic cache partitioning for CMPs
Transactions on high-performance embedded architectures and compilers III
A majority-based control scheme for way-adaptable caches
Facing the multicore-challenge
| Hi-index | 0.00 |
This paper presents a control mechanism for dynamically way-adaptable caches. The mechanism uses the local and global information about the locality of reference during execution. As the local information, the cache access pattern is evaluated based on the statistics of the LRU (Least-Recently Used) states of cache entries referenced. If the memory accesses are concentrated on and near the most recently used entries, the mechanism knows that the locality of reference is very high and there is room to decrease the number of ways activated to fit the current locality. On the other hand, if the accesses are widely distributed from the most recently used entries to the least recently used ones, the mechanism understands that more ways are needed to improve the performance as long as the resources are available. In addition, to examine the global behavior of the locality of reference, an n-bit state machine like n-bit branch predictors is introduced into the mechanism. The state machine traces a sequence of cache resizing requests and evaluates its stability across the execution time. Therefore, the state machine helps the mechanism avoid unstable actions for enabling/disabling cache ways when the locality shows the highly irregular behavior. The experimental results indicate that an n-bit asymmetric state machine using the LRU status information works well to appropriately control cache ways even in the case of the benchmarks with highly-irregular access behaviors in cache references.