A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs

Authors:
Isao Kotera;Ryusuke Egawa;Hiroyuki Takizawa;Hiroaki Kobayashi
Affiliations:
Tohoku University, Sendai, Japan;Tohoku University, Sendai, Japan;Tohoku University, Sendai, Japan;Tohoku University, Sendai, Japan
Venue:
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
Year:
2007

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Abstract

Chip Multiprocessor (CMP) architectures are the principal trend in current and future microprocessor design, and on-chip shared cache mechanisms play a key role to realize low-power and high performance CMPs. In this paper, we propose a way-allocatable shared cache mechanism, which can achieve both high performance and cache power reduction by using cache partitioning and power gating. We evaluate the performance of our cache mechanism by a cycle accurate simulator, in terms of performance and energy consumption. The performance evaluation results show that the proposed mechanism can properly adjust the control policy from a performance-oriented configuration to a energy-oriented one. The proposed cache mechanism with a performance-oriented parameter setting can reduce energy consumption by 20% while keeping the performance, and the cache with an energy-oriented parameter setting can reduce 54% energy consumption with a performance degradation of 13%.