Activity-driven clock design for low power circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage power optimization with dual-Vth library in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
A high-level register optimization technique for minimizing leakage and dynamic power
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Power optimization with power islands synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With the migration to Deep Sub-Micron (DSM) process technologies, the static power (leakage) has become the major contributor to the design's overall power consumption. In this work, we will show experiments that illustrate the significant increase in the ratio of the leakage to the total power as the DSM process nodes shrink. We will also present a novel high-level design/synthesis method, called Power Islands, that minimizes the leakage in the circuit by partitioning it into islands. Each island is a cluster of logic whose power can be controlled independent from the rest of the circuit, and hence can be completely powered down when all the logic contained within it is idling. The partitioning is done in such a way that the components with maximally overlapping lifetimes are placed on the same island. A main benefit of Power Islands is the elimination of leakage in inactive components during the power down cycles of the islands, and hence a decrease in circuit's power consumption.The effectiveness of the proposed technique is demonstrated through several examples implemented with 4 different feature sizes: 180 nm, 130 nm, 100 nm and 70 nm. These experiments showed improvements in leakage ranging from 41% to 80% at 70 nm due to Power Islands.