An exact algorithm for low power library-specific gate re-sizing
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Journal of the ACM (JACM)
IMPACT: a high-level synthesis system for low power control-flow intensive circuits
Proceedings of the conference on Design, automation and test in Europe
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Maximum Leakage Power Estimation for CMOS Circuits
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level synthesis algorithms for low power asic design
High-level synthesis algorithms for low power asic design
Minimizing total power by simultaneous Vdd/Vth assignment
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Leakage power analysis and reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal-induced leakage power optimization by redundant resource allocation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Scheduling with integer time budgeting for low-power optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A variation aware high level synthesis framework
Proceedings of the conference on Design, automation and test in Europe
Variation-aware resource sharing and binding in behavioral synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Power optimization with power islands synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Behavioral level dual-Vth design for reduced leakage power with thermal awareness
Proceedings of the Conference on Design, Automation and Test in Europe
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
HLS-dv: a high-level synthesis framework for dual-Vdd architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
| Hi-index | 0.00 |
In this paper we address the problem of module selection during high-level synthesis. We present a heuristic algorithm for leakage power optimization based on the maximum weight independent set problem. A dual threshold voltage (Vth) technique is used to reduce leakage energy consumption in a data flow graph. Experiments are performed on a data-path dominated test suite of six benchmarks. Our approach achieves an average of 70.9% leakage power reduction, which is very close to the optimal results from an Integer Linear Programming approach.