Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An exact algorithm for low power library-specific gate re-sizing
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Leakage-tolerant design techniques for high performance processors
Proceedings of the 2002 international symposium on Physical design
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Temperature-aware resource allocation and binding in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Leakage power optimization with dual-Vth library in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Minimizing total power by simultaneous Vdd/Vth assignment
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Adaptive chip-package thermal analysis for synthesis and design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A combined gate replacement and input vector control approach for leakage current reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design space exploration using time and resource duality with the ant colony optimization
Proceedings of the 43rd annual Design Automation Conference
Thermal-induced leakage power optimization by redundant resource allocation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An integrated approach to thermal management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage power analysis and reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Dual-Vth design is an effective leakage power reduction technique at behavioral synthesis level. It allows designers to replace modules on non-critical path with the high-Vth implementation. However, the existing constructive algorithms fail to find the optimal solution due to the complexity of the problem and do not consider the on-chip temperature variation. In this paper, we propose a two-stage thermal-dependent leakage power minimization algorithm by using dual-Vth library during behavioral synthesis. In the first stage, we quantitatively evaluate the timing impact on other modules caused by replacing certain modules with high Vth. Based on this analysis and the characteristics of the dual-Vth module library, we generate a small set of candidate solutions for the module replacement. Then in the second stage, we obtain the on-chip thermal information from thermal-aware floorplanning and thermal analysis to select the final solution from the candidate set. Experimental results show an average of 17.8% saving in leakage power consumption and a slightly shorter runtime compared to the best known work. In most cases, our algorithm can actually find the optimal solutions obtained from a complete solution space exploration.