Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
High Level Synthesis for Peak Power Minimization Using ILP
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Leakage power optimization with dual-Vth library in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
Proceedings of the conference on Design, automation and test in Europe
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Scheduled voltage scaling for increasing lifetime in the presence of NBTI
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Facelift: Hiding and slowing down aging in multicores
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Gate replacement techniques for simultaneous leakage and aging optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Leakage power analysis and reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
M-IVC: Applying multiple input vectors to co-optimize aging and leakage
Microelectronics Journal
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Aging effects (such as Negative Bias Temperature Instability (NBTI)) can cause the temporal degradation of threshold voltage of transistors, and have become major reliability concerns for deep-sub-micron (DSM) designs. Meanwhile, leakage power dissipation becomes dominant in total power as technology scales. While multi-threshold voltage assignment has been shown as an effective way to reduce leakage, the NBTI-degradation rates vary with different initial threshold voltage assignment, and therefore motivates the co-optimizations of leakage reduction and NBTI mitigation. This paper minimizes leakage power during high-level synthesis of circuits with bounded delay degradation (thus guaranteed lifetime), using multi-Vth resource libraries. We first propose a fast evaluation approach for NBTI-induced degradation of architectural function units, and multi-Vth resource libraries are built with degradation characterized for each function unit. We then propose an aging-bounded high-level synthesis framework, within which the degraded delays are used to guide the synthesis, and leakage power is optimized through the proposed aging-aware resource rebinding algorithm. Experimental results show that, the proposed techniques can effectively reduce the leakage power with an extra 26% leakage reduction, compared to traditional aging-unaware multi-Vth assignment approach.