High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
An iterative improvement algorithm for low power data path synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Early evaluation techniques for low power binding
Proceedings of the 2002 international symposium on Low power electronics and design
Statistical Timing Analysis of Combinational Circuits
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
High-level synthesis for low power based on network flow method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Adjustable robust solutions of uncertain linear programs
Mathematical Programming: Series A and B
Timing
Temperature-aware resource allocation and binding in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Leakage power optimization with dual-Vth library in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
Circuit optimization using statistical static timing analysis
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A statistical framework for post-silicon tuning through body bias clustering
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Proceedings of the conference on Design, automation and test in Europe
Timing variation-aware high-level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A variation aware high level synthesis framework
Proceedings of the conference on Design, automation and test in Europe
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
System-level mitigation of WID leakage power variability using body-bias islands
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Timing variation-aware task scheduling and binding for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing variation-aware high-level synthesis considering accurate yield computation
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Performance yield-driven task allocation and scheduling for MPSoCs under process variation
Proceedings of the 47th Design Automation Conference
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Scheduling and resource binding algorithm considering timing variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Low-power resource binding by postsilicon customization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level leakage variability mitigation for MPSoC platforms using body-bias islands
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3DHLS: incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Cost-effective lifetime and yield optimization for NoC-based MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Static statistical MPSoC power optimization by variation-aware task and communication scheduling
Microprocessors & Microsystems
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection techniques in high level synthesis use worst case delay/power information to perform the optimization, and therefore may be too pessimistic such that extra resources are used to guarantee design requirements. Parametric yield, which is defined as the probability of the synthesized hardware meeting the performance/power constraints, can be used to guide design space exploration. The parametric yield can be effectively improved by combining both design-time variation-aware optimization and post silicon tuning techniques (such as adaptive body biasing (ABB)). In this paper, we propose a module selection algorithm that combines design-time optimization with post-silicon tuning (using ABB) to maximize design yield. A variation-aware module selection algorithm based on efficient performance and power yield gradient computation is developed. The post silicon optimization is formulated as an efficient sequential conic program to determine the optimal body bias distribution, which in turn affects design-time module selection. The experiment results show that significant yield can be achieved compared to traditional worst-case driven module selection technique. To the best of our knowledge, this is the first variability-driven high level synthesis technique that considers post-silicon tuning during design time optimization.