Proceedings of the 6th international workshop on Hardware/software codesign
A comparison of list schedules for parallel processing systems
Communications of the ACM
Journal of Parallel and Distributed Computing
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Critical path driven cosynthesis for heterogeneous target architectures
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Introduction to Data Mining, (First Edition)
Introduction to Data Mining, (First Edition)
Variation-aware task allocation and scheduling for MPSoC
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Characterizing chip-multiprocessor variability-tolerance
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Timing variation-aware task scheduling and binding for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms
Proceedings of the Conference on Design, Automation and Test in Europe
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
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With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling process to improve its performance yield when building today's multiprocessor system-on-a-chip (MPSoC). Existing solutions assume that the execution times of tasks performed on different processors are statistically independent, which ignores the spatial correlation characteristics for systematic variation. In addition, a unified task schedule is constructed at design stage and applied to all products with various variation effects, which restricts the maximum performance yield that can be achieved for MPSoC products. To tackle the above problems, in this paper, we present a novel quasi-static scheduling algorithm. Based on a more accurate performance yield estimation method, a set of variation-aware schedules is synthesized off-line and, at run time, the scheduler will select the right one based on the actual variation for each chip, such that the timing constraint can be satisfied whenever possible. Experimental results demonstrate the effectiveness.