An architectural co-synthesis algorithm for distributed, embedded computing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hierarchical algorithms for assessing probabilistic constraints on system performance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Estimating probabilistic timing performance for real-time embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Task scheduling and voltage selection for energy minimization
Proceedings of the 39th annual Design Automation Conference
IEEE Transactions on Parallel and Distributed Systems
Probabilistic performance guarantee for real-time tasks with varying computation times
RTAS '95 Proceedings of the Real-Time Technology and Applications Symposium
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical gate sizing for timing yield optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Journal of VLSI Signal Processing Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Timing variation-aware task scheduling and binding for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
OpenMP Support for NBTI-Induced Aging Tolerance in MPSoCs
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms
SOC'09 Proceedings of the 11th international conference on System-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance yield-driven task allocation and scheduling for MPSoCs under process variation
Proceedings of the 47th Design Automation Conference
A Metric for Quantifying Similarity between Timing Constraint Sets in Real-Time Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Process variation-aware routing in NoC based multicores
Proceedings of the 48th Design Automation Conference
Variability-tolerant workload allocation for MPSoC energy minimization under real-time constraints
ACM Transactions on Embedded Computing Systems (TECS)
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Profit maximization through process variation aware high level synthesis with speed binning
Proceedings of the Conference on Design, Automation and Test in Europe
HW-SW integration for energy-efficient/variability-aware computing
Proceedings of the Conference on Design, Automation and Test in Europe
Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Static statistical MPSoC power optimization by variation-aware task and communication scheduling
Microprocessors & Microsystems
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As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. As a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable [1]. In this paper, we propose a variation-aware task allocation and scheduling algorithm for Multiprocessor System-on-Chip (MPSoC) architectures to mitigate the impact of parameter variations. A new design metric, called performance yield and defined as the probability of the assigned schedule meeting the predefined performance constraints, is used to guide the task allocation and scheduling procedure. An efficient yield computation method for task scheduling complements and significantly improves the effectiveness of the proposed variation-aware scheduling algorithm. Experimental results show that our variation-aware scheduler achieves significant yield improvements. On average, 45% and 34% yield improvements over worst-case and nominal-case deterministic schedulers, respectively, can be obtained across the benchmarks by using the proposed variation-aware scheduler.