Hierarchical algorithms for assessing probabilistic constraints on system performance

Authors:
G. de Veciana;M. Jacome;J.-H. Guo
Affiliations:
Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas;Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas;Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

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Abstract

We propose an algorithm for assessing probabilistic performance constraints for systems including components with uncertain delays. We make a case for designing systems based on a probabilistic relaxation of performance constraints, as this has the potential for resulting in lower silicon area and/or power consumption. We consider a concrete example, an MPEG decoder, for which we discuss modeling and assessment of probabilistic throughput constraints.