A Formal Definition of Data Flow Graph Models
IEEE Transactions on Computers
High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Relations and graphs: discrete mathematics for computer scientists
Relations and graphs: discrete mathematics for computer scientists
Specification and design of embedded systems
Specification and design of embedded systems
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Methodology for behavioral synthesis-based algorithm-level design space exploration: DCT case study
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hierarchical algorithms for assessing probabilistic constraints on system performance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Data-Driven and Demand-Driven Computer Architecture
ACM Computing Surveys (CSUR)
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Digital Signal Processing: A Practical Approach
Digital Signal Processing: A Practical Approach
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Specification and Design of Embedded Hardware-Software Systems
IEEE Design & Test
PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Embedded Architecture Co-Synthesis and System Integration
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Hierarchical algorithms for assessing probabilistic constraints on system performance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
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Incorporating algorithm and architecture level design space exploration in the early phases of the design process can have a dramatic impact on the area, speed, and power consumption of the resulting systems. This paper proposes a framework for supporting system-level design space exploration and discusses the three fundamental issues involved in effectively supporting such an early design space exploration: definition of an adequate level of abstraction; definition of good fidelity system-level metrics; and definition of mechanisms for automating the exploration process. The first issue, the definition of an adequate level of abstraction is then addressed in detail. Specifically, an algorithm-level model, an architecture-level model, and a set of operations on these models, are proposed, aiming at efficiently supporting an early, aggressive system-level design space exploration. A discussion on work in progress in the other two topics, metrics and automation, concludes the paper.